[Chip Expert: AI Computing Power Bottleneck Shifting from Chips to Packaging, Interconnects, and Storage] Beating AI Newsflash: Veteran chip designer and hardware analyst 'Mr. Bubble' stated in an interview on the Frictionless Podcast that the core bottleneck of AI computing infrastructure is shifting from simply enhancing chip performance to advanced packaging, system interconnect latency, and storage hierarchy management. Mr. Bubble believes that the rapid rise in advanced process costs, coupled with limited improvements in transistor density, poses economic challenges to the traditional Moore's Law. Instead of continuing to shrink process nodes, the industry is increasingly connecting multiple chips into a single computing system through advanced packaging. He pointed out that the fundamental unit of AI computing power in the future may no longer be a single chip or server but rather a complete rack or even multiple racks, with PCB, packaging, and interconnect capabilities becoming critical limiting factors. In terms of storage, he noted that as AI inference context windows expand, massive historical context data should not all occupy expensive HBM. The industry may increasingly adopt flash memory offloading, keeping high-frequency data in HBM while migrating low-frequency context to larger-capacity, lower-cost storage tiers. He further predicted that 3D DRAM could become a key direction for next-generation memory technology. Regarding AI infrastructure investment, Mr. Bubble suggested that as preloading and decoding gradually adopt a decoupled architecture, the importance of system-level hardware design will further increase. He also stated that compared to directly betting on large model companies, enterprises with capabilities in hardware, packaging, storage, and other critical infrastructure may play a more enduring role in the AI industry chain. [Original Link]