[Huawei Semiconductor Chief Warns: NVIDIA Chip Scaling Nearing Physical Limits, Crossing the Threshold Could Trigger an 'Avalanche'] BlockBeats reports that on August 4, Huawei's Chief Scientist of Semiconductors and one of the key pioneers behind the Ascend AI chips, Liao Heng, issued a warning during a recent public interview. He stated that Western chip giants, represented by NVIDIA, are approaching physical limits in their pursuit of more powerful processors—'Scaling by continuously adding compute chips and more HBM inevitably has a ceiling. The industry is still advancing, but once this physical limit is crossed, an avalanche will occur.' Liao Heng likened the entire AI value chain to an '18-layer pagoda,' contrasting it with NVIDIA CEO Jensen Huang's 'layered cake' framework. He emphasized that China needs to build synergy at every layer, particularly fostering close collaboration between chip manufacturers and AI model developers. Liao also revealed that Huawei is set to release its first smartphone chip designed under the Tau Scaling Law framework, utilizing LogicFolding technology. Once organizations like SemiAnalysis and TechInsights conduct teardown analyses, 'the world will later this year clearly understand how this alternative path helps narrow the gap.' Tau Scaling Law is an innovative design concept proposed by Huawei, focusing on improving the transmission speed between components of a computer system as the inherent advantages of chip miniaturization gradually diminish. Liao further praised DeepSeek founder Liang Wenfeng, stating that the key to training top-tier models with extremely low computational power by 2025 lies in innovations in model architecture design. He compared China's AI innovation to maximizing the use of space in a small apartment, while Western counterparts operate in more spacious villas. Liao noted that Huawei is also developing AI chips that better support efficient architectures through a co-design mechanism between chips and models. 'We must invest more effort in design, trading higher complexity for lower computational resource consumption.'