整理 & 编译：深潮 TechFlow

Guest: Dylan Patel, Founder of SemiAnalysis

Host: None (Independent commentary video)

Podcast Source: SemiAnalysis

Original Title: Did China just beat Intel?

Broadcast Date: July 20, 2026

Disclosure Statement: This video interprets the first public report from the STEEL teardown lab under SemiAnalysis, directly promoting its paid teardown products. SemiAnalysis competes directly with the established teardown giant TechInsights (the latter is being sold by private equity, and SemiAnalysis's revenue has surpassed TechInsights). The following content faithfully presents its technical analysis and does not represent the position of this publication.

Key Summary

SemiAnalysis dissected Huawei's latest flagship chip, Kirin 9030, and measured the finest metal line widths under an electron microscope. The result was unexpected: the minimum metal spacing of SMIC's third-generation 7-nanometer process N+3 is only 32.5 nanometers, narrower than Intel's latest 18A process used in Panther Lake, which has a spacing of 36 nanometers. A Chinese foundry cut off from the supply of EUV lithography has surpassed Intel's leading node in wiring density.

However, SemiAnalysis itself stated in the report that this number was deliberately selected. N+3 has indeed caught up with TSMC's N6 in terms of transistor density, at the cost of quadruple patterning, more photomasks, higher costs, and lower yield; performance and power consumption have fallen behind, with the Kirin 9030 roughly comparable to three-year-old Android flagships. In plain terms, Chinese chips are still several years behind, but being behind does not mean being stuck. Export controls have not stopped China; they simply posed a different problem. The last statement in the video is worth pondering: China does not need to catch up with TSMC; it just needs to be good enough that it no longer needs TSMC.

Highlights of the Discussion

About that astonishing headline number

• "A Chinese foundry cut off from the most advanced tools and without EUV has a wiring density about 10% tighter than Intel's leading EUV node."
• "Minimum metal spacing is only part of density; it does not indicate how fast logic switches or how much power is consumed."
• "That number is real; it's just that what it measures does not determine who wins."

About achieving EUV-level density without EUV

• "EUV allows you to roughly make a fine pattern in one shot. Without EUV, you need more creativity."
• "The more steps you take, the more layers of photomasks, more alignments, and more chances for errors increase costs and lower yield."
• "SMIC indeed achieved EUV-level density through brute force with DUV, but at the cost of more photomasks, more steps, and more chances of failure. This does not count as a tie."

About catching up on density while lagging in performance

• "Lines have gotten thinner, and density has increased, but the physics of the node has not kept up."
• "Apple's tiny efficiency cores surprisingly outperform Huawei's big cores in integer performance, using only 1 watt compared to Huawei's big cores at 4.5 watts."
• "SMIC has been chasing the wrong dimension."

About why everyone still fears China

• "Being a few years behind and being completely stagnant are two different things."
• "You can keep climbing the wall, but the wall will only get steeper."
• "Export controls have not stopped China; they have simply presented a different problem for China to solve."

About the real trump card

• "China does not need to become TSMC to be meaningful. They just need to be good enough that they no longer need TSMC."

How big is the gap without EUV in China?

Currently, the world of semiconductor manufacturing is divided into two camps: those with EUV lithography machines and those without. Losing EUV is clearly a disadvantage for China, but how big is this manufacturing gap?

This is a HiSilicon Kirin 9030, the chip inside Huawei's latest flagship phone. A few weeks ago, SemiAnalysis dissected it, placed it under an electron microscope, and measured the finest wires inside the chip, that is, the metal spacing. The results were unexpected.

The internal minimum metal spacing of the Kirin 9030 is only 32.5 nanometers, smaller than that of Panther Lake, which uses Intel's brand-new 18A node. A Chinese foundry cut off from the most advanced tools and without EUV has a wiring density about 10% tighter than Intel's leading EUV node.

This video aims to clarify three things: how SMIC achieved this without EUV; why thinner lines do not necessarily mean better performance; and why, even when several years behind, China has begun to become an important player at the wafer manufacturing table.

STEEL Teardown Lab: Where do these numbers come from?

First, let’s talk about where these numbers and measurements come from, because this aspect itself is quite cool.

SemiAnalysis established a teardown lab called STEEL, which stands for SemiAnalysis Teardown Engineering and Evaluation Lab. Teardown, as the name suggests, involves physically disassembling the world's most advanced chips and reverse-engineering how they are made. For roughly the last twenty years, only one company was capable of doing this at scale; now that is no longer the case.

So everything you see next, including cross-sections, line widths, and transistor counts, comes directly from STEEL.

On the "operating table" is the Kirin 9030, Huawei's flagship SoC, based on SMIC's third-generation 7-nanometer process, internally codenamed N+3, which is currently China's most advanced process.

However, looking at a number alone is meaningless; it needs a reference point. Therefore, STEEL also dissected another chip, MediaTek Helio G99, a budget smartphone SoC made using TSMC's N6 process. The reason is simple: TSMC's N6 and SMIC's 7-nanometer N+3 are roughly in the same tier, at the same level of nodes. One is made using the best Western equipment, and the other is made in China under export controls. Placing both chips under the same microscope, the results hopefully can tell a complete story.

N+3 vs. N6: Density has indeed caught up

Don't rush to compare with Intel 18A; first, look at N+3 against N6. Did SMIC's N+3 achieve a finer metal spacing than N6? The simple answer is yes.

The minimum metal spacing measured inside the Kirin 9030 is 32.5 nanometers, while the minimum metal spacing based on N6 Helio G99 is 40 nanometers, which is a considerable difference.

However, "thinner lines" refers to density, indicating how much logic can fit in a square millimeter, and does not directly indicate the overall quality of the chip or this node. Minimum metal spacing is just one part of the equation, and it does not indicate how fast logic switches or how much power it consumes.

Looking purely at density, SMIC has indeed achieved this. N+3 has about 113 million transistors per square millimeter, while TSMC's N6 has about 108 million. So it’s true that SMIC's latest DUV node genuinely exceeds an EUV node in density.

How to achieve EUV-level density without EUV: Multiple patterning and DTCO

So, how did they achieve EUV-level density without EUV? There are two tricks, each with its own costs.

The first trick is multiple patterning. EUV lets you create a relatively fine pattern in one shot. Without EUV, you need to be more creative. The approach is to first create a rough pattern, deposit a thin layer of spacer along the edges, then etch, and use these spacers as a new, finer mask. It’s somewhat like drawing a line, tracing its two edges to create two thinner lines, and then repeating the process. Doing it once is called self-aligned double patterning (SADP), and it’s called self-aligned because the spacer itself is defined along the existing pattern. Doing it twice is quadruple patterning (SAQP). SMIC's finest layers require four iterations of that version.

The more iterations you do, the more layers of photomasks you add, more alignments, and more chances for errors increase costs and lower yield. "You know I don't like low yields."

The second trick is Design Technology Co-Optimization (DTCO), which means no longer treating chip design and manufacturing processes as two separate issues but optimizing them together. In practice, this compresses the layout of the unit area itself: each transistor uses fewer fins, connecting the gate contacts directly above the active gate instead of shifted to the side, or reducing the isolation distance between adjacent units.

Each DTCO technique can reclaim a bit of area, but each also makes the transistor more fragile and harder to model. Thus, while SMIC has indeed caught up with TSMC's EUV nodes in density, it relies on using more photomasks, more steps, and more chances of failure to brute-force DUV. This does not count as a tie.

Catching up on density, but performance and power consumption have lagged

Density looks impressive, but this is also where it starts to break down. Because area is the easiest dimension to modify, power consumption and performance are much harder.

Since Dennard scaling laws broke down in the mid-2000s, the old rule named after Robert Dennard (that transistor miniaturization would lead to faster and more power-efficient devices) is no longer valid. This kind of free scaling has ended; with DTCO, speed and efficiency must be fought separately; you can’t have both.

This is exactly what can be seen in SMIC's N+3 node. The Kirin 9030 Pro is a relatively dense chip, but its performance is only comparable to three-year-old Android flagships. When compared to the best from Apple, Qualcomm, MediaTek, and Samsung today, it isn't in the same league at all. The efficiency gap is even larger than the speed gap.

A typical example is Apple's tiny efficiency cores, the really small ones. The integer performance of Apple's E cores outperforms Huawei's big prime core while consuming only about 1 watt compared to Huawei's big core at 4.5 watts. In terms of performance per clock, Huawei's prime core roughly matches the level of the Arm Cortex-X2, a design from 2021. Frankly speaking, this is quite respectable engineering. But Apple's M1 from 2020, at a similar power consumption level, still outperforms it by about 35% per clock. And the current leading edge is several steps ahead of both.

Thus, while N+3 has a slight advantage in density over TSMC's N6, N6 has already been out for several years. Apple and Qualcomm are already working on chips based on N4 and N3, which are denser with better voltage-frequency curves. Chips based on N2 will also be coming later this year. They have more transistors, and each switches faster at lower power consumption. SMIC is somewhat chasing the wrong dimension. Lines may be thinner, and density may be higher, but the physics of the node has not kept pace.

Comparing with Intel 18A: The headline is real, but what it measures is not decisive

Comparing N+3 with Intel's latest 18A shows an even more pronounced contrast. On paper, 18A can achieve an M0 metal spacing of 32 nanometers, which matches N+3. However, on Panther Lake, Intel used many high-performance cells, widening the metal spacing to 36 nanometers.

According to design goals, a looser M0 spacing can also bring benefits in terms of costs and yield because it lowers complexity. But the premise is that you have the freedom to decide where and how to shrink, which means the headline "tighter than Intel" is true, but it cannot speak to competitiveness. The numbers are real; it's just that what they measure does not determine who wins.

In terms of transistor density, 18A clearly outpaces N+3, even with slightly wider metal spacings. Because, just as a chip is not just about density, density is not just about M0 metal spacing. Back-side power delivery allows you to reduce the front-side metal spacing since the power connections come in from the back of the chip.

Why do people still fear China: Being behind does not mean being stagnant

So why does everyone still fear China? Because being a few years behind and being completely stagnant are two different things.

SMIC still has room for growth with DUV. Finer lower metal layers, such as M0 being only the first layer of metal, still have many layers to go. Shorter units and tighter gate spacing. On paper, the future N+4 could roughly catch up to TSMC N5 level density, and the N+5 with back-side power delivery could reach Intel 18A level density. But, let’s say it again, it’s just about density; power consumption and performance cannot catch up.

The key is that the difficulties accumulate. Each optimization looks reasonable on its own, but without EUV to layer them all together, each new node is slower, more expensive, and less forgiving than the last. You can keep climbing the wall, but the wall will only get steeper.

Export controls have not stopped China; they have simply changed the problem that China is solving.

Moreover, knowledge is diffusing. SMIC has been asked to license N+2 and N+3 to other domestic foundries. If this process experience flows into AI accelerators, the bottleneck will no longer be a single foundry that can be sanctioned, but an entire ecosystem.

The real victory: Being good enough to no longer need TSMC

To quickly review SMIC's 7-nanometer N+3 node. Without EUV and without back-side power delivery. Higher complexity, higher costs; the efficiency gap is real. According to every critical frontier metric, China has not been closing the gap with TSMC, Intel, or Samsung. This point is basically clear under the microscope.

However, being "behind the frontier" and being "irrelevant" are two different things. If domestic chips are good enough to be used in mobile phones, inference, networking, or any security-sensitive fields, then that's a win. China does not need to become TSMC to be meaningful. They just need to be good enough that they no longer need TSMC.

Everything in the video comes from STEEL: die annotation, block-level analysis, direct cuts through logic and memory with electron microscope cross-sections. There’s a lot more in the video that wasn’t expanded on: complete process flows, material analysis, fin measurements, package dissections. For a deep dive into SMIC's latest node, you can check out SemiAnalysis's teardown article; the link is in the video description.

This is STEEL's first public report, and there will certainly be more to come. If you enjoy this kind of content, you can subscribe. "I would love to hear your thoughts on this one. Is good enough to not need TSMC really good enough? Let me know in the comments."