Written by: Rita

Trends Introduction

In May, Japan's shipment value of packaging substrates (rigid module substrates) grew by 36% year-on-year, reaching 27.8 billion yen, setting a new historical high. This figure alone is striking, but Nomura Securities believes that the more noteworthy aspect is the technological route competition beneath the surface: the packaging structure of Rubin Ultra may shift from the four-die solution announced at the GTC conference to a dual-module structure, with TSMC and Intel engaged in more intense competition around 2.5D, 3D, and 3.5D packaging. The increase in shipment volume is in the present, but the outcome will be determined by technological iterations over the next two years.

May Data Sets New High, Both Volume and Price Speak

Nomura Securities cited data from Japan's Ministry of Economy, Trade and Industry's "Industrial Production Survey": In May, the shipment value of packaging substrates reached 27.8 billion yen, surpassing the previous high of 27.3 billion yen set in March, with a year-on-year increase of 36%. In terms of volume, the shipment area per square meter increased by 10% year-on-year; in terms of price, the average price per square meter reached 1.356 million yen, a further increase of 23% compared to the previous high of 1.226 million yen set in April. Demand is not only increasing in volume but is also skewing towards high-end products.

Nomura Securities infers that demand for NVIDIA's Rubin packaging will truly ramp up this summer (by August at the latest), with related packaging substrate shipments gradually climbing. The currently observed 36% growth rate is only the prelude.

Four Die or Dual Module? Changes in Rubin Ultra Packaging Structure

The most critical technical judgment in the report: There is a consensus forming in the market that the packaging structure of Rubin Ultra may change from the four-die solution announced by NVIDIA at the GTC conference in March to a dual-module structure, with two bare chips combined in a 3D stacking manner within each module. Some opinions also suggest that the Feynman architecture may adopt a similar dual-module design.

Why the change? The core bottleneck lies in the denser wiring and more pins of HBM4; integrating a large intermediary layer with over 5.5 times the photomask area with HBM4 presents a steep increase in technical difficulty. TSMC may choose 3.5D packaging as a transition solution in its future roadmap, combining 3D stacking and 2.5D packaging, and advance towards more aggressive integration after the technical feasibility of large intermediary layers becomes clearer.

Intel EMIB-T Makes Its Debut: HBM4 Stacking Possible Without Intermediary Layer

At the American Electronic Components and Technology Conference, Intel released a technical paper on EMIB-T. This is a 2.5D packaging solution with the key feature of not using an intermediary layer.

Intel disclosed that EMIB-T will be ready for mass production by 2026, targeting a product size of 8 times the photomask area, with a packaging size of 120×120 mm, capable of integrating up to 12 HBM4 chips, using a four-die structure. Compared to the previous generation EMIB, EMIB-T introduces silicon vias and MIM capacitors, improving the voltage drop of the internal power supply network by 68-80%. This improvement is crucial; EMIB faced limitations in promoting AI accelerator packaging due to the prominent issue of power supply voltage drop.

Nomura Securities believes that Intel is building an ecosystem to compete with TSMC through EMIB-T, but TSMC still holds advantages in power management and heat dissipation capabilities, especially as the 3DFabric Alliance has already gathered numerous partners in equipment and materials.

The Four Battlefields that Determine Victory

The report points out that the core technologies in the next-generation packaging competition are four: power supply, heat dissipation, CPO, and 3D stacking (hybrid bonding). Whomever can establish ecological advantages in these four areas will dominate the AI accelerator packaging.

In the short term, the high growth in packaging substrate shipments will continue, driven mainly by the mass production of Rubin and the penetration of HBM4. In the medium term, the customer structure and product positioning of packaging substrate manufacturers will depend on which industry leaders and technological routes they can align with. The differences between TSMC's and Intel's routes will directly affect the specifications, layers, sizes, and thermal designs of upstream materials.

Trends Perspective

This report breaks down monthly shipment data, revealing an escalating technological route war beneath the surface. Packaging substrates are different from ordinary PCBs; in the AI era, their performance is directly determined by the packaging architecture adopted by customers. The structural adjustments of NVIDIA's Rubin will influence the entire chain, including TSMC, Intel, substrate manufacturers, and HBM suppliers.

Although Nomura Securities did not provide specific stock ratings, it highlighted a clear judgment: In the next phase, the excess returns in the packaging substrate industry will come from whether they can bind technological routes to leading clients, as relying solely on industry prosperity is insufficient.

Disclaimer

This article is a compilation and interpretation of a third-party brokerage research report (Nomura Securities, July 14, 2026) by Trends Research. The ratings, target prices, profit forecasts, and related judgments quoted in the text are the views of the brokerage firm's analysts, representing their institution's position and do not represent the views of Trends Research, nor do they constitute any investment advice.

Markets carry risks, and decisions should be made independently. This article should not be used as the basis for buying or selling any securities.