Author: Bibi News
AI stock god Leopold went from 200 million to 13 billion, the white-haired stock god generated an annualized return of 225 times, and Chen Liwu has invested in 159 IPOs, all relying on the same framework: finding bottlenecks.
Leopold founded a fund with $225 million, reaching $5.5 billion in 12 months, and has now expanded to $13 billion. The bottleneck he bets on is the AI physical infrastructure, including electricity, computing power, memory, and optical interconnection.
His investment portfolio does not include a single share of NVIDIA, instead, he shorted the entire chip sector using $8.46 billion in put options.
The white-haired stock god who turned down an offer from NVIDIA when its shares were at $6, selects small-cap stocks based on the perilla leaf theory, claiming an annualized return of 225 times. The bottleneck he bets on is CPO optical interconnection, InP substrates, optical transceivers, and other upstream AI optical communication supply chains.
Intel CEO Chen Liwu emphasized this theory further in an interview on the No Priors podcast on June 18, 2026. Before leading Intel, Chen Liwu served as CEO of Cadence for twelve years, during which the stock price rose 32 times.
At the same time, he is also one of the most active venture capitalists in the semiconductor field, personally investing in over 200 semiconductor companies, including 159 IPOs. The bottlenecks he bets on cover EDA, GaN/SiC/InP, and other new materials as well as optical interconnection.
A circuit board showing the AI hardware supply chain
Pick up any AI accelerator's circuit board.
Before it is manufactured, designers need to use EDA tools to verify the layout of hundreds of billions of transistors, replace silicon, which is reaching its physical limits, with new materials like InP, GaN, and SiC, and use helium to protect each precise step in the lithography and etching process.
On the board, GPU chips are stacked with HBM memory, completed through TSMC's CoWoS or Intel's EMIB for advanced packaging. The GPU sets the upper limit of computing power, HBM determines whether the computing power can be released, and packaging determines whether they can be assembled together.
Between boards, thousands of such accelerators need to work together. Copper cables are approaching their physical bandwidth limits, and optical interconnection is taking over.
Around the board, 48V needs to be dropped down to less than 1V required by the GPU, generating heat at every step of conversion; a cabinet consumes 120kW of power, traditional air cooling can no longer keep up, and liquid cooling is becoming the standard.
Outside the board, all of this requires electricity. The power consumption of an AI data center is equivalent to that of a medium-sized city, while expanding the power grid and building new generation facilities takes years.
This is the complete picture of the nine bottlenecks. Let’s break them down one by one.
Before the board
EDA: A single tape-out failure can cost tens of millions of dollars
All chips must go through EDA for design and verification before manufacturing, with verification accounting for 60%-70% of the entire chip development cycle.
AI accelerators integrate hundreds of billions of transistors, layered with HBM, 3D stacking, and advanced packaging, leading to increasing design complexity, but the computational efficiency of EDA tools has not kept pace. If verification fails, a re-tape-out is required, and the cost of failure can exceed tens of millions of dollars.
In 2025, the EDA market size is expected to be about $14.5 billion and to approach $18 billion by 2026. Synopsys, Cadence, and Siemens together capture over 65% of the market share. Chen Liwu served as CEO at Cadence for twelve years, making him more aware of the pricing power of this segment than most investors; he describes EDA as a gold mine. Cadence has already improved the design convergence speed by five times, and Siemens's AI system achieves a ten-fold acceleration on certain tasks.
New materials: Silicon can no longer bear the load; five materials are stepping in
Traditional silicon-based materials are gradually reaching their performance ceiling in power consumption, heat dissipation, and optical communication. Five new materials are emerging as breakthroughs: GaN (high-frequency power devices), SiC (high voltage and large current), InP (optical communication), synthetic diamond (thermal conductivity), and glass substrates (advanced packaging).
800G and 1.6T optical modules rely on InP materials, and the current demand gap for AI optical interconnection is about 40%-60%. Glass substrates are seen as the next generation of advanced packaging, with both Intel and TSMC accelerating production. Wolfspeed and Infineon are investing over $15 billion in SiC capacity from 2025-2027.
Helium: Non-renewable; a supply cut leads to an immediate production halt
In early 2026, an incident occurred that most investors completely overlooked: supply disruptions at Qatar's Ras Laffan affected 27%-30% of global helium supply, with spot prices temporarily rising by 40%-100%. The South Korean semiconductor industry relies on Qatar for about 64.7% of its helium, putting Samsung and SK Hynix's HBM production lines at risk of supply shortages.
Helium is used throughout the EUV lithography, etching, deposition, and wafer cooling processes; it is non-renewable and lacks alternatives. The semiconductor industry accounts for about 24% of global helium consumption, which is expected to rise to 30% by 2030. More troublesome is that the helium consumption for the 2nm process will increase by about 20% compared to 3nm. The more advanced the process, the more it relies on a diminishing resource.
Samsung has launched a helium recycling system, and TSMC's advanced production lines achieve a recovery rate of 80%-90%. However, recycling can only alleviate, not resolve, the fundamental problem: supply is concentrated in a few sources, and the construction of new gas sources takes years.
On the board
HBM: Supply not meeting demand; DRAM prices have doubled in two years
HBM provides GPUs with high-speed data transmission capabilities, and supply has been tight for a long time, becoming a core bottleneck for AI server shipments. Memory is what is lacking most.
The global HBM market size for 2026 is expected to be around $9.2 billion, and it may grow to nearly $70 billion by 2035, with a compounded annual growth rate of over 25%. SK Hynix, Samsung, and Micron dominate the market, with SK Hynix becoming a core supplier for NVIDIA due to its leading capacity, while Samsung and Micron are accelerating the expansion of HBM3E and HBM4 production.
The GPU determines the upper limit of computing power, and HBM determines whether this computing power can be released.
Advanced packaging: The GPU is made, but packaging is backlogged
Advanced packaging integrates the GPU and HBM into a complete AI accelerator, with TSMC's CoWoS being the most mainstream solution. Even if the GPU and HBM have been produced, they cannot be converted into computing power without completing the packaging.
TSMC's CEO publicly stated that CoWoS capacity is "extremely tight, sold out for 2026." Capacity has increased from around 35,000-40,000 pieces/month at the end of 2024 to a target of 120,000-140,000 pieces/month by 2026, but demand is growing even faster. Global demand for CoWoS is expected to reach nearly 1 million wafers by 2026, with NVIDIA accounting for about 60% and locking in a large amount of capacity through long-term contracts.
Intel bets on EMIB and glass substrate solutions in an attempt to compete with TSMC in packaging, and packaging companies like ASE and Amkor are also ramping up production.
Between boards
Interconnection/Photonics: Copper cables can no longer bear the load; optical interconnection takes over
Large model training requires thousands or even tens of thousands of GPUs to cooperate. No matter how powerful a single GPU's computing power, if the data transmission speed between chips cannot keep up, the actual utilization rate of the entire cluster will be dragged down. The currently mainstream copper cable interconnection solutions are approaching their physical bandwidth limits, and high-speed interconnection chips and new interconnection architectures are becoming the focus of capital-intensive investment.
Photonic solutions are the next generation fix for interconnection bottlenecks. Electrical signals face problems of signal attenuation and heat generation at long distances and high-density transmission scenarios, while optical signals possess physical advantages in both aspects. Silicon photonics and CPO (Co-Packaged Optics) are expected to reduce interconnection power consumption by 30%-50%, but manufacturing processes, packaging integration, and cost control are not yet mature, leading to a significant gap between production capacity and AI cluster demand. The optical interconnection market is expected to be around $15 billion by 2025, reaching $43 billion by 2034.
Jensen Huang has invested in almost all companies working in optical interconnection. Since 2026, NVIDIA has invested over $6.5 billion in photonics: about $2 billion each to Lumentum and Coherent, and $500 million to Ayar Labs to lay out the silicon photonics route.
Around the board
Power conversion: Dropping from 48V to 1V; traditional silicon devices cannot withstand
AI servers need to convert power from 48V or even higher to less than 1V needed by the GPU through multiple stages. Traditional silicon-based power devices are inefficient in high-power scenarios, while GaN and SiC are becoming the next generation solutions.
onsemi estimates that in the next-generation 1MW AI rack, the value of power semiconductors will double from about $50,000 to $100,000. The GaN/SiC power device market is expected to be around $2 billion in 2025-2026, and to exceed $8 billion by 2030, with an annual growth rate of over 20%.
Infineon has acquired GaN Systems to complete its product line, and Navitas has introduced GaN power solutions for AI data centers, while onsemi, Wolfspeed, and STMicroelectronics are also accelerating the expansion of SiC capacity.
Liquid cooling: A cabinet consumes 120kW, and air cooling can no longer handle it
New generation AI server cabinets, represented by the NVIDIA GB200 NVL72, have power consumption exceeding 120kW. If this heat is managed solely by fans, the space and noise requirements in the data center would spiral out of control. Liquid cooling is becoming the standard solution for the next generation of AI data centers.
The global liquid cooling market for data centers is projected to be about $5 billion in 2025 and expected to grow to $27.1 billion by 2035. The adoption rate of liquid cooling in newly built AI data centers is expected to increase from about 35% in 2025 to about 55% by the end of 2026.
NVIDIA promotes liquid cooling architectures in its Blackwell and Rubin platforms, while Microsoft, Google, Amazon, and Meta are accelerating adoption in newly constructed data centers. In terms of chip-level heat dissipation, Chen Liwu has laid out initiatives in synthetic diamond to leverage its high thermal conductivity to solve local heat concentration issues of high-power chips.
Outside the board
Electricity: The power grid cannot keep up; data centers are queuing for power
There are already numerous data center projects in the United States facing delays due to insufficient power grid access.
Amazon, Microsoft, Google, and Meta's capital expenditures in 2026 are expected to total $700 billion, with a significant portion flowing towards AI infrastructure and energy support. The traditional power grid's expansion rate cannot keep up with demand, prompting technology companies to shift towards long-term power purchase agreements, natural gas power generation, and nuclear energy as alternatives.
Leopold believes that a battle for all remaining power contracts of this century and every transformer is unfolding behind the scenes in Silicon Valley. His judgment is: the real bottleneck in the AI era is not algorithms, but electricity.
Williams invested $5.1 billion to build modular natural gas power facilities, while GE Vernova's gas turbine orders are backlogged to a level of 100GW; NVIDIA is pushing small modular reactors through its NVentures investment in TerraPower, and the Stargate project is also exploring nuclear power supply.
Compared to other technological bottlenecks, building electricity infrastructure involves grids, land, and approvals, leading to longer construction cycles that are also more difficult to replicate quickly.
How long can this framework be used?
How long can this bottleneck investment framework be utilized? It depends on when supply catches up with demand.
From the production capacity construction schedule, the second half of 2027 is the first supply release point: SK Hynix's M15X factory is planned to commence production in mid-2027, and Micron's Singapore and Taiwan factories are also targeting 2027. The white-haired stock god predicts that the photonic super cycle will also begin to take volume in mid-2027. The year 2028 is the second wave: the Samsung Pyeongtaek P5 factory, the SK Hynix American Indiana factory, and the Micron Hiroshima factory will come online. Chen Liwu's judgment is: "There will be no relief before 2028."
However, the launch of new capacities does not mean the disappearance of bottlenecks. Each generation of GPUs has its HBM demand doubling, and NVIDIA’s next Rubin architecture will further amplify the demand for HBM4; moreover, hyperscale cloud providers have already locked in a large amount of new capacity through long-term contracts, limiting the shares available in the open market.
In 2017-2018, DRAM prices soared dramatically, Samsung significantly expanded production, and capital expenditure rose by over 50%. After new capacities were released in 2019, prices collapsed, leading to industry-wide losses. From capacity investment to price reversal took 18 months.
This cycle's scale is much larger than the previous one. DRAM prices are expected to rise by about 275%-300% from 2025 to 2027, three times the increase of 2017-2018, and this occurs on a threefold revenue base. The market capitalizations of the three memory manufacturers, SK Hynix, Samsung, and Micron, have all exceeded $1 trillion, with HBM profit margins hitting 60%-70%, far exceeding traditional DRAM. According to the same 18-month window calculation, the end of 2028 to mid-2029 will be a period that requires high vigilance.
What truly needs to be monitored is this signal: if by then the growth rate of AI capital expenditures slows down while the three manufacturers release new capacities simultaneously, the supply-demand relationship could quickly reverse, turning a bottleneck into a surplus, and pricing power could shift from suppliers back to buyers.
Leopold's actions suggest he is already preparing for this scenario. While betting long on power and infrastructure, he is using $8.46 billion in put options to short the semiconductor sector. His judgment is that once the AI infrastructure construction cycle peaks, fierce competition among chip companies will compress profit margins, but the scarcity of electricity and physical infrastructure will be more persistent and harder to replicate.
Until then, the supply-demand imbalance in this chain shows no signs of easing.
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