[TSMC's A14 Process to Shrink SRAM Cell Area to Below 0.017 Square Micrometers, Resuming Minimization After 8 Years] According to BlockBeats, on October 26th, TSMC plans to shrink the area of high-density 6T SRAM (Static Random Access Memory) cells to below 0.017 square micrometers in its A14 process, which aims for mass production in 2028. This breaks the long-standing stagnation at approximately 0.021 square micrometers since the N5 process in 2020. The report states that TSMC is expected to announce the relevant research results by the end of the year. Based on currently disclosed data, the SRAM cell area of the A14 process is expected to surpass that of Intel's 18A process; the latter previously announced a high-density SRAM cell area of 0.021 square micrometers. Since Samsung has not yet disclosed the specific SRAM cell size of its latest process, a direct comparison is currently difficult. SRAM is a key storage component used for high-speed caching within CPU, GPU, and AI accelerator chips. With smaller cell sizes, more cache can be accommodated within the same chip area, helping to alleviate data access bottlenecks in AI chips and improve performance and energy efficiency. TSMC stated that the A14 process aims to offer a 10% to 15% performance improvement, a 25% to 30% reduction in power consumption, and an approximately 20% increase in chip density compared to the N2 process. The process is currently progressing towards its 2028 mass production target, but final yield, cost, and customer adoption remain to be confirmed. [Original Link]