律动BlockBeats
律动BlockBeats|Jul 21, 2026 10:25
Samsung's hybrid bonding technology is expected to be used for Nvidia's next-generation AI accelerator Feynman, and the chip will adopt customized HBM According to BlockBeats, on July 21st, Samsung Electronics has started building a Die to Wafer hybrid bonding production line at its P5 factory in Pyeongtaek, with the goal of advanced packaging for next-generation HBM and logic semiconductors. The preferred core equipment supplier is Besi from the Netherlands, and Samsung plans to purchase about 50 hybrid bonding machines, each costing approximately 6 billion Korean won (about 4.3 million US dollars), which is twice the price of its competitors. However, due to Samsung's slow progress in negotiating customized modifications to the device architecture, and Besi's simultaneous supply to TSMC and Micron, they are cautious about changing the device solely for Samsung. Samsung is simultaneously considering local alternative solutions: its subsidiary SEMES has completed the development of D2W hybrid bonding machines and sent samples for verification earlier this year; Hanhua Semitech completed the development of the second generation "SHB2 Nano" in February and sent samples to SK Hynix in April. Its cluster system integrating EFEM, plasma activation, and cleaning modules has formed differentiated competitiveness. This technology uses mixed copper bonding instead of traditional hot press bonding, which can directly bond copper and dielectric materials, greatly reducing the interconnect length. The core application scenario is customized HBM - stacking HBM DRAM layers vertically on logic dies containing customer computing circuits and IP to form 3D system level packaging. Citrini analyst Jukan stated that hybrid bonding is expected to be used for Nvidia's next-generation AI accelerator Feynman, which will adopt customized HBM, and the technology's implementation time has been postponed from HBM4E. Samsung expects to achieve large-scale applications internally around 2029 to 2030, coinciding with Nvidia Feynman's expected window.
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