By carefully reading the signed paper by Huawei's He Tingbo, we can understand the "Tao (τ) Law". From this paper, we can see the five core points of the "Tao (τ) Law" in the theory of scaling time. However, the closer you look, the more you will find that the underlying logic of Huawei, Nvidia, and TSMC is consistent in their future evolutionary iteration paths. Let's talk in detail about my understanding. 1. First, let's talk about the five core points of Tao's Law 1) LogicFolding/Logical Folding. The definition given in the article is: LogicFolding is a design method that divides digital circuits, analog circuits, and storage circuits into vertically stacked active layers, optimizing performance, power consumption, and area by shortening critical path routing. It's not just about making the packaging thicker, nor is it a regular 2.5D Chiplet, but it's closer to folding the originally two-dimensional tiled logic circuit vertically 2) Unified Bus, Traditional AI clusters require multiple layers of protocol stacks: PCIe, NVLink or proprietary interconnect, Ethernet or InfiniBand, RDMA, software messaging, etc. Each layer of protocol conversion will increase serialization, DMA buffering, handshake, and latency. The goal of Unified Bus is to replace these protocol stacks with a single protocol that runs both inside and between chassis, and expose native memory semantics throughout the entire system. The paper states that this can reduce remote access latency from the tens of microseconds of traditional protocol stacks to about 100 nanoseconds, and reduce system τ along the main communication axis by about 500 times; In terms of rack scale, making the system closer to a structurally consistent single machine is internally referred to as System as One Chip. This is actually a system collaboration at the chip server rack data center level. 3) Hi ONE Near Package Optical Engine According to He Tingbo's paper, when the bandwidth of a single AI chip reaches the Tb/s level, copper cable wiring will encounter volume SerDes、 Limitations on heat dissipation, power supply, and reliability. Huawei's Hi ONE is a near encapsulated optical interconnect node engine. The article states that a single Hi ONE module can provide 8 Tb/s bandwidth, reducing the SerDes transmission distance from about 100 centimeters to about 5 centimeters, while expanding the transmission distance between panels from less than 1 meter to 100 meters. This indicates that Huawei's system level roadmap also incorporates optical interconnect into the core architecture, not just external optical modules, but closer to near package optical I/O. 4）3D Folding The paper argues that there is a geometric contradiction in traditional 2.5D AI chips: the logic chip area increases by N ², so the computing power increases by area; But resources such as HBM, SerDes, and power supply mainly enter along the packaging edge, and bandwidth, I/O, and power capacity only increase by circumference N. The computing power expands by N ², and the edge resources expand by N, and the gap between the two will become increasingly large. The function of 3D Folding is to transfer resources that were originally located at the edge to the surface or vertical direction: power is supplied through the back and integrated voltage regulator, high-speed storage is mixed with logic through bonding, and optical I/O is encapsulated through Hi ONE, allowing for synchronous expansion of memory, interconnects, power, and logic. Huawei sees 3D folding as the core topology for AI accelerators to continue expanding after 2030. 5) Reintegration of logic and memory The paper also has an important industry judgment: in the past few decades, CPU and memory have developed in a decoupled manner; But the AI era is reversing this decoupling. The reason is that AI workloads have extremely high requirements for memory bandwidth, latency, power consumption, and packaging. HBM、 Hybrid bonding and 3D stacked SRAM both indicate that data transfer is as important as computation itself, and logic and memory are moving towards tight physical integration. The paper further concludes that with the integration of logic and memory, the influence in the supply chain will tilt towards memory and packaging suppliers. 2. The paper also lists the future challenges of Tao's law as follows: 1) The EDA toolchain is insufficient. Traditional EDA is a tool in the two-dimensional era, mainly optimizing between area, timing, and power consumption. Full scale LogicFolding requires tools to treat multiple stacked chips as a continuous design entity, with cross layer layout at unit granularity rather than module granularity, and unified sign off for vertical interconnects, TSV, KOZ exclusion areas, and inter wafer process deviations. The paper states that Huawei has preliminary internal tools, but native, open, multi physics, and 3D native toolchains will still be one of the most important empowerment investments in the next decade. 2) Process deviation between wafers. LogicFolding may bond wafers from different batches or even different nodes. Threshold voltage, driving current, and interconnect RC deviation can affect clock distribution and hold time margin, requiring intelligent redundancy, adaptive compensation, and τ sensing signature. 3) Vertical interconnection is not free. Hybrid bonding and TSV both bring resistance, capacitance, and area overhead, and the keep out zone of TSV also squeezes standard cells. Therefore, logic folding must prove that the benefits of shortening horizontal connections outweigh the costs of increasing vertical interconnects. 4) τ is the law of time, not the law of energy consumption. The paper acknowledges that if the speed is increased by 10 times but the power consumption is also increased by 10 times, the system may still exceed the power constraint. Therefore, τ scaling must be matched with energy optimization, including near package/co package optics, backside power supply, in memory computing, dynamic voltage and frequency regulation, etc. Overall, it can be seen from this paper that the "Tao (τ) Law" is a systematic design innovation+3D integration+packaging/bonding process, rather than the traditional "process node breakthrough". The 'Tao Law' is more like a shift from single point process innovation to systematic and system level improvement. Against the backdrop of limited advanced processes and declining economic viability of Moore's Law, Huawei has proposed a system level scaling strategy for the post Moore's era: using the τ time constant as a unified metric, and leveraging LogicFolding, Unified Bus, Hi ONE, 3D Folding, logic memory fusion, and τ native EDA to shift performance improvement from single point process competition to full stack system engineering. 3. Why is it said that Huawei, Nvidia, and TSMC have the same underlying logic in their future evolutionary iteration paths? From a personal perspective, this is fundamentally similar to the direction of TSMC Advanced Packaging and Nvidia NVLink/HBM/CPO/AI Factory. Everyone is solving the same problem: data movement is too slow, too expensive, and too power consuming. This is actually the ultimate consensus for global semiconductor giants to jointly move towards the 'post Moore era'. Both Huawei's "Tao Law" and the movements of international giants are putting effort into the overall system: 1) TSMC: It has long realized that advanced processes are too expensive and there are physical bottlenecks in yield, so it vigorously develops advanced packaging technologies such as CoWoS and SoIC, building multiple chiplets together like building blocks. 2) Nvidia: The current AI computing monsters (such as the Blackwell architecture and subsequent products) have advantages not only in the manufacturing process of a single GPU core, but also in the high integration of massive high bandwidth memory (HBM) and optical chips through NVLink high-speed interconnect technology, breaking down the "memory wall" and "communication wall". 3) Huawei: Faced with extreme pressure from the external environment, it must rely on advanced packaging, new materials, optoelectronic co packaging (CPO), and extremely powerful system engineering capabilities to forcefully "assemble" comprehensive performance equivalent to 1.4nm in the absence of cutting-edge manufacturing equipment. Of course, there are also differences. For example, TSMC's advanced packaging response is: "How can I integrate multiple dies, HBMs, chiplets, and silicon interlayers RDL、 Can mixed bonding be used to create mass-produced, testable, and yield controlled products? ” The answer to Huawei's "Tao Law" is: "How can I reduce τ from devices, circuits, chips, and the entire system chain when the process is limited, and continue to improve performance, energy efficiency, and density? ” The two are essentially interconnected because they are both addressing issues such as slow data transfer, high power consumption, and excessive space occupation. But they are not things at the same level. TSMC is more like a platform for underlying manufacturing/packaging capabilities, while Huawei is more like a system architecture and design methodology. Looking at Nvidia's most typical route in recent years, it is "not just doing GPUs, but doing the entire AI computing system". The Nvidia GB200 NVL72 is not a story of a single GPU, but rather a rack scale architecture: 72 Blackwell GPUs and 36 Grace CPUs form a 72-GPU domain through NVLink, appearing like a huge GPU to the outside world, and providing 130TB/s of low latency GPU communication bandwidth through NVLink Switch. The Nvidia model is very similar to the system level thinking of "Tao's Law": don't just look at the peak computing power of a single chip, but also look at the data movement efficiency between GPUs, GPUs CPUs, GPUs memory, and cabinets. 4. Investment logic: Infrastructure for the system level engineering roadmap in the post Moore era. Huawei's' Tao Law 'is not a breakthrough in single chip manufacturing, but a system level engineering route in the post Moore era. It benefits not a single wafer fab, but advanced packaging, probe testing EDA、 The complete infrastructure includes equipment materials, high-speed interconnection, optical interconnection, heat dissipation, power supply, and system software. Why? Because once the goal shifts from "making transistors smaller" to "shortening paths and making systems faster", the value of the industry chain will spread from single point wafer manufacturing to: Advanced packaging: bring chiplets, HBMs, and logic chips closer together; Probe card/testing equipment: Multiple die, multi-layer, and complex packaging require higher testing requirements; Packaging substrate/PCB/connector: high-speed signal integrity is more critical; Optical module/silicon optical/CPO: board level and cabinet level data transmission moves from electrical to optical; EDA/IP: Insufficient 2D layout, requiring 2.5D/3D/packaging/thermal/power collaborative design; Heat dissipation/liquid cooling/power supply: The higher the integration, the more difficult it is to heat and power supply; System software/bus/interconnection protocol: Hardware stacking is not enough, scheduling and communication protocols also need to be restructured. So in terms of investment, we need to find: who can shorten the data paths between chips, within chips, between chips and memory, and between servers, and who can gain an advantage in the industry chain. The future progressiveness depends more on "how far the data will go, how fast it will go, how much power it will consume, and whether the system can work together". Huawei's "Tao Law", TSMC Advanced Packaging, and NVIDIA AI Factory are essentially all working on this issue