Huawei University of Science and Technology collaborates to break through Nvidia's monopoly, with the Ascend A3 running a large model and expert calculations accelerating by 58% According to Beating monitoring, in the evolution of large-scale MoE architecture, using domestically produced Ascend chips to train large models has become a key direction for building autonomous and controllable AI computing power. However, mainstream large model frameworks are mostly developed based on the NVIDIA CUDA ecosystem, and when directly ported to the Ascend platform, they are prone to challenges such as uneven hardware queue scheduling and low computing power utilization. University of Science and Technology of China, Huawei, and Peking University have jointly launched the HyperParallel MoE compilation scheduling framework, which performs tile level control on the unique hardware queue of Ascend A3, aiming to break through the energy efficiency bottleneck of heterogeneous computing power in parallel scheduling. The Ascend A3 has two types of cores, AIC is responsible for matrix multiplication, and AIV handles vector computation and communication. But under traditional operator serial scheduling, the two types of cores can only work alternately and idle alternately. Experimental data shows that when running the 671B DeepSeek style large model in a 256 node cluster, the AIC utilization rate is only 67%, and 39% of expert routing communication delays are exposed on critical computing paths. There are three changes to the HyperParallel MoE core. Firstly, design a single-sided write primitive driven by AIV to trigger computation upon arrival of data tiles, without waiting for the entire batch to arrive. Secondly, introduce dependency aware tile task generation to unify and abstract communication and computation operators. Thirdly, a static scheduler is used to pre generate task sequences, driving two types of cores in parallel within a single kernel, and utilizing high-speed L2 cache to share intermediate results, reducing the latency of writing back and reading HBM slow memory. Tests have shown that under 64 node balanced routing, the core module responsible for expert computation (MoE FFN) has reduced latency by about 36%, which is equivalent to a maximum increase of 58% in data processing speed (i.e. 1.49 to 1.58 times faster). In the end-to-end operation of the whole machine, the single step training speed has also been synchronously improved by 8% to 9%. This indicates that the actual energy efficiency of Ascend depends not only on hardware specifications, but also on whether the AIC/AIV core can be efficiently scheduled by the compiler and runtime. [Original link]