Huawei proposes the τ scaling law, Kirin chip uses LogicFolding for the first time this autumn According to Beating monitoring, Huawei announced the τ scaling law at the 2026 IEEE International Circuit and Systems Symposium ISCAS, proposing to replace geometric scaling with time scaling to find new paths for the evolution of chips and electronic systems. Based on the time scaling path, Huawei has launched the LogicFolding architecture and announced that the Kirin chip released in the fall of 2026 will adopt the LogicFolding architecture for the first time. Traditional Moore's Law relies on the continuous reduction of transistor geometry, but advanced processes are facing physical limitations and a decrease in cost-effectiveness. The core of the τ scaling law is to systematically shorten the propagation time of signals and data in devices, circuits, chips, and systems, thereby improving performance, energy efficiency, and equivalent transistor density. At the device layer, Huawei reduces the time constant τ by optimizing the resistance and parasitic capacitance of transistors and interconnects. At the circuit layer, LogicFolding breaks the boundaries of traditional circuit layouts, shortens critical path wiring, and reduces the resistance capacitance load of signal propagation. At the chip level, Huawei enhances parallel efficiency through collaborative design of software, architecture, and chips. At the system level, the Unified Bus interconnect protocol is designed for SuperPoD to achieve unified memory addressing and native memory semantics, in order to reduce system communication latency. Huawei claims to have designed and mass-produced 381 chips based on the τ scaling law over the past 6 years, covering scenarios such as mobile phones and AI computing. The company expects that by 2031, high-end chips designed based on the τ scaling law will reach 14 Å, which is the equivalent transistor density of 1.4 nm process. Huawei has currently disclosed its design methods and roadmap goals, but has not provided independent performance testing data for LogicFolding on Kirin chips. [Original link]