Yuntian Lifei: Introducing 3D Stacked Storage Architecture into Reasoning Chip under Development. According to JinShi Data on May 12th, Yuntian Lifei disclosed in its investor relations activity record that the reasoning chip being developed by the company adopts GPNPU architecture as its core technology route. The main technical highlights include four aspects: firstly, GPGPU level universal programming capability: targeting the pain point of "usability" of domestic chips, GPNPU architecture emphasizes compatibility and migration support for mainstream CUDA and other ecosystems to reduce the threshold for customer model deployment and migration; The second is the NPU core with ultimate energy efficiency: deeply optimizing the inference efficiency and energy efficiency ratio to enhance the cost-effectiveness of the inference side; The third is to introduce a 3D stacked storage architecture: adopting a 3D stacked storage architecture to achieve higher bandwidth and lower access latency, break through the "memory wall", and improve inference efficiency; The fourth is the architecture of computing power building blocks: The company continues its exploration in domestic processes over the past five years, using the "computing power building block" architecture to construct rack level Scale up supernodes using next-generation chips, in order to meet the inference needs of trillion or even trillions of MoE architecture models. The company's goal through this technology roadmap is to exponentially reduce token costs and accelerate the large-scale and inclusive implementation of large-scale model applications.