Industry research: The invisible watershed of LSA --2nm As advanced processes approach physical limits, "heat" becomes one of the most critical variables, and even a slight temperature deviation can easily lead to unacceptable yield. The significance of LSA annealing equipment has changed in advanced nodes. In the previous manufacturing process, ion implantation is an unavoidable step. It is responsible for injecting doped atoms into silicon, defining the electrical properties of the device, while inevitably damaging the lattice structure. The function of annealing is to accomplish two things: repairing the lattice and activating doping. The traditional path is furnace tube or rapid thermal annealing (RTA), which heats the wafer as a whole to rearrange atoms at high temperatures. But the problem is that this heating is global, with a time of seconds or even longer, and doping undergoes diffusion while being activated, resulting in wider junctions and blunted boundaries. In the 28nm and 14nm era, this diffusion can still be tolerated. But below 7nm, especially after transitioning from FinFET to GAA (Gate Al Around), the device size approaches the physical limit, and any additional diffusion will directly erode the performance window. The problem has changed from 'requiring annealing' to 'requiring an annealing without side effects'. LSA heats the wafer surface instantaneously in nanoseconds to microseconds, which can be higher than traditional annealing, but due to its extremely short duration, thermal diffusion is suppressed in a very shallow range. Subsequently, rapid cooling activates doping and repairs the lattice, but the position hardly migrates, resulting in the formation of extremely shallow and steep junctions. This directly corresponds to lower leakage, higher switching speed, and more controllable electric field distribution. Looking at the evolution of device structures, FinFET solves the problem of continued scaling after the failure of planar devices; GAA enhances gate control capability by wrapping channels on all four sides, allowing advanced nodes to still move forward for a period of time; In the future, CFETs (Complementary FETs) will continue to increase density through vertical stacking after horizontal compression is no longer possible. In this process, the structure continues to evolve, but the constraints are tightening, and the "hot budget" gradually becomes the hardest boundary. The core changes of GAA are thinner channels, smaller spacing, and more complex structures. Any additional thermal diffusion will directly alter the geometric and electrical properties of the device. Source/rain doping will invade the channel and rapidly deteriorate the short channel effect; The spacing and stress distribution between nanosheets are disturbed, leading to a decrease in the ability to control the electric field; The contact area itself is extremely small, and slight diffusion can cause significant resistance changes. Under this structure, thermal diffusion is no longer a performance loss, but a structural damage. This is also the reason why traditional annealing begins to fail. You can still use it to activate doping, but the cost is to "thermally blur" the designed device. The final result is a transistor that can conduct electricity but deviates from the design window. LSA precisely solves this contradiction. It decouples "temperature" and "time": allowing for extremely high temperatures, but compressing the action time to a scale where diffusion has not yet occurred; At the same time, through line beam scanning, it only acts on the surface area to avoid heating of deep structures. The three conditions of high temperature, extremely short time, and local control are almost only applicable simultaneously on LSA in existing heat treatment schemes. Therefore, in the FinFET era, LSA was more of a performance enhancement tool, while in GAA, its role became a "structural feasibility tool". As nodes enter 3nm, 2nm, or even smaller, heat treatment is no longer a flexible process step that can be adjusted, but has become a core variable that limits device design space. The importance of LSA has therefore been repriced, gradually shifting from "optional" to "default configuration". GAA will still be the main trend for the next 5 to 8 years, but its marginal returns are decreasing. As the size approaches 2nm and below, the problem begins to shift towards material and physical limits: the channel cannot infinitely thin, contact resistance rapidly increases, and power consumption no longer decreases proportionally. The industry's answer is to shift towards a three-dimensional structure, namely CFET, which stacks NMOS and PMOS vertically and requires density in the vertical direction after being constrained laterally. But CFET brings a new constraint: heat. GAA is still a single-layer structure with a high tolerance for high-temperature treatment; In CFET, any high-temperature process may potentially damage another layer of structure that has already been completed. The traditional RTA method of "whole piece heating" is starting to fail because its thermal diffusion range is too large to achieve interlayer isolation. This makes LSA even more important in the future, as its nanosecond time scale and nanoscale heating depth enable it to handle only a single layer without affecting the upper and lower layer devices. This selective heat treatment capability is the foundation for the establishment of the CFET process. This change is also reshaping the competitive landscape. From a device perspective, LSA remains a multi player market, with core vendors including Veeco Instruments Inc., Applied Materials, and SCREEN Holdings. SCREEN relies on installed capacity and historical verification to dominate, Applied Materials leverages platform capabilities to bind with customers to form system advantages, and Veeco achieves breakthroughs in advanced node critical processes through LSA. But real competition is not just about devices. The first layer is direct competition between equipment manufacturers; The second layer is process route competition, which involves the trade-off between technologies such as LSA and RTA; The third layer is system level competition, which refers to who can integrate equipment, materials, and processes into the complete process. In the GAA stage, this competition is more reflected in device performance and parameter capabilities; Entering the CFET stage, competition will shift towards deep collaboration with wafer fabs, and the moat will shift from a single device to a system capability of "equipment+process+materials". From the customer import situation, Veeco has completed the most critical step, as its LSA equipment has entered the leading advanced logic factory and become a standard equipment for mass production in some processes. This means that the technology has passed the strictest validation and has the potential to expand with increasing production capacity. But this kind of import is still focused on local processes rather than comprehensive dominance. In the storage field, including DRAM and HBM, LSA is still in the evaluation stage and has not yet entered mass production. Therefore, the competition of LSA is essentially that whoever can do better in details such as temperature control, scanning uniformity, and stress management has a better chance of entering the standard process path of advanced nodes. Overall, in the evolution from FinFET, GAA to CFET, LSA has completed the transformation from a performance optimization tool to a structural implementation foundation. The real bottleneck in the next stage is not just the structure or alignment accuracy, but whether doping activation and defect repair can be completed under the premise of multi-layer stacking without damaging other layer structures. This will determine the upper limit of advanced processes and also determine where the value will be concentrated. Disclaimer: I hold the assets mentioned in the article, and my views are biased and not investment advice