Regarding NVIDIA's upcoming Feynman architecture, we have organized the collaborative relationship between three types of memory SRAM, HBM5, and HBF in the Feynman architecture. Many people are confused by these dazzling memories, let me guide you through them. 1、 3D SRAM: Nanosecond level 'thermal memory' synapse (Physical extension of computing core) Core functions: Eliminate memory access latency: Provide a response of<1ns, store the instantaneous activation values and instruction fragments within a single cycle. Cache Pool: As a bridge between HBM5 and Tensor Core, it is directly stacked above the GPU core through SoIC (Hybrid Bonding) to ensure zero idle of computing units. Technical specifications: Bandwidth/Capacity: on-chip bandwidth>150 TB/s, single chip capacity 1.5 GB -3 GB. Process: Adopting 2nm/3nm process, SoIC stacking is led by TSMC. Manufacturer pattern: Hynix and Micron focus on high-density 6T SRAM cells to optimize thermal power consumption; Samsung utilizes the advantages of IDM to independently develop customized SRAM wafers. 2、 HBM5: The "Warm Memory" Backbone of Feynman Architecture (In memory computing and 3D bonding peak) Core functions: Model complete set carrier: stores full weights and active KV cache. In memory computing (PIM): The underlying Base Die is customized by NVIDIA and supports direct preprocessing such as vector addition on the storage side, freeing up GPU computing power. Technical specifications: Performance: Single chip bandwidth of 15-20 TB/s, single card capacity of up to 1 TB. Interconnection: Fully transition to Hybrid Bonding, supporting 20-24 layer stacking. Manufacturer's path: SK Hynix: Smooth transition to hybrid bonding with Advanced MR-MUF. Samsung: The most aggressive route, leading full hybrid bonding with over 16 layers. Micron: focuses on low-power control (low pJ/bit). SanDisk/Western Digital: Accumulating high-speed logical layer IP through CBA technology. 3、 HBF (High Bandwidth Flash): Agent's "Cold Memory" Warehouse The ultimate solution for long context storage Core functions: ICMS platform core: dedicated to storing inactive KV cache, solving the dialogue memory of AI agents spanning several months. Cold and hot swapping: Implementing lossless data migration with HBM5 through CXL 3.1 protocol. Technical specifications: Performance: Read rate of 1.6-2 TB/s (close to HBM), capacity of up to 8 TB-16 TB. Durability: Built in hardware wear leveling engine, with a lifespan of 5 times that of regular NAND. Manufacturer's path: SanDisk/Western Digital: Leader in directly bonding HBF controllers underneath BiCS NAND. SK Hynix: Developing HBF-NAND stack, striving for uniformity in external dimensions with HBM. Samsung: launches low latency Z-NAND hybrid to narrow the performance gap with DRAM. 4、 Collaboration Relationship Summary: AI Agent Task Flow In the Feynman architecture of NVIDIA's AI Agent task flow, the three constructed a memory loop from "neural reflection" to "deep thinking": 3D SRAM processes instantaneous activation values and instructions in real-time within the chip with a delay of<1ns, ensuring zero pause in the computing core; HBM5, as the power heart inside the package, carries the full model weights and active KV cache through a bandwidth of 5 TB/s, maintaining the coherence of inference logic; HBF, on the other hand, serves as a long-term memory repository at the system level, utilizing a massive storage space of 8-16 TB to store inactive contexts. Through the CXL 3.1 protocol and HBM5, it achieves hot and cold data exchange, jointly supporting the intelligent agent's ability to handle complex tasks across time and space.